Section: New Results

Data-Aware Process Networks

Participants : Christophe Alias, Alexandru Plesco.

The following results concern the applied research activities directly linked to the Zettice start-up (see Section  7.3 ), which aims at applying polyhedral techniques to high-level circuit synthesis (HLS). Following the guidelines of Inria DTI, as this research aims to be transferred, these results are not published before being “protected” or exploited. An Inria patent deposit is currently processed.

• Data-aware process networks (DPN). This is the intermediate representation of the HLS flow. DPN is a parallel execution model fitting the hardware constraints of circuit synthesis, in which the data transfer and the synchronizations are made explicit. We formally described the DPN model and a translation scheme from C programs, and we showed the consistency in the meaning where any terminating sequential program is translated to an equivalent DPN, guaranteed to be deadlock free.

• Front-end analysis. We designed many program analyses to produce a quality DPN from a C program:

  • Throughput optimization. A I/O scheme has been designed, with the corresponding compiler analysis, to minimize the I/O traffic with the external memory. This allows us to balance efficiently the spilling of temporary value to the memory, and the local buffer size. This scheme impacts the DPN structure itself.

  • Communication vectorization. The matrix structure of the memory allows us to load data by chunks. A polyhedral analysis has been designed to solve this issue.

  • Synchronization scheme. As parallel units need to communicate intermediate results, synchronizations must be ensured.Unlike KPN, DPN do not use FIFO, but buffers, which required an efficient synchronization mechanism.

• Back-end analysis. Once generated, a DPN must be mapped to an FPGA. This raises many interesting issues:

  • Pipeline completion. Data paths make an extensive use of pipelined operators, which delays the signal. An algorithm has been designed to enforce the time coherence of signals.

  • Polyhedral units. DPNs make an extensive use of piece-wise affine functions, which must be mapped properly to ensure the efficiency of the whole system. A preliminary algorithm has been designed to reach a correct trade-off between critical path size and LUT usage.

All these analyses have been fully implemented. The tool Dcc (DPN C Compiler) implements all the front-end analyses. The tool IceGEN implements the back-end analysis.